So SystemVerilog is just Verilog, right ?

Not really! SystemVerilog is a superset of Verilog. SystemVerilog (SV) has constructs for RTL design (synthesizable), assertions (SVA) and testbench (sb-tb).
    Thus one could compile and run all existing Verilog code with SV mode switched on in the simulator. However the reverse is not true. To adopt systemverilog one could use the following approach.
1. Start using SV design  constructs to make code more concise (always *, always_ff, etc) and modular (interfaces )
2. Deploy assertions (SVA) to reduce debug time in case of test failure.
3. SV-tb to write automated testbench and track progress using coverage.

Most Vendors are now providing methodology on top of SV language support to enable engineers to benefit from the newly added language constructs. VMM, OVM, UVM.... you pick. Example, the methodology of how, where and when to add assertions is as important as the actual SVA code itself. Reason being the performance hit due to extra code being added needs to be counterbalanced with the advantages of adding SVA. BUT, there is always as but, one must pay extra attention to the SVA syntax since it is relatively easy to write a performance hog SVA code. Cliff Cummings has a paper on this subject