SystemVerilog (SV) is an now a IEEE standard (P1800) hence the official LRM needs to be purchased from from IEEE. However the accellera version, that was donated to IEEE, is available for free download at http://www.eda-stds.org/sv/SystemVerilog_3.1a.pdf .
The 3.1a standard is good enough for practical reference on language syntax etc. Though it is not the recommended getting started point, there are some engineers who would still like to reference the LRM time to time ( I know, I have actually met a few of those).
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