Where is UVM 2.0?

 Several customer have asked me about UVM2.0, well it is not here yet. Accellera  released UVM1.1b in May 2012. As per the  release notes
 "Release 1.1b contains mostly fixes to errata with limited API changes. There are several API changes that were approved case by case by the VIP TSC. "

So must current UVM users can continue to use existing testbench code as it is. Please do read the release notes to make sure you are aware of the changes from uvm1.1a to uvm 1.1b. Also as per accellera website, the next majour uvm relesae will be uvm 1.2 and not 2.0.

So SystemVerilog is just Verilog, right ?

Not really! SystemVerilog is a superset of Verilog. SystemVerilog (SV) has constructs for RTL design (synthesizable), assertions (SVA) and testbench (sb-tb).
    Thus one could compile and run all existing Verilog code with SV mode switched on in the simulator. However the reverse is not true. To adopt systemverilog one could use the following approach.
1. Start using SV design  constructs to make code more concise (always *, always_ff, etc) and modular (interfaces )
2. Deploy assertions (SVA) to reduce debug time in case of test failure.
3. SV-tb to write automated testbench and track progress using coverage.

Where can I find SystemVerilog LRM

SystemVerilog (SV) is an now a IEEE standard (P1800) hence the official LRM needs to be purchased from from IEEE. However the accellera version, that was donated to IEEE, is available for free download at http://www.eda-stds.org/sv/SystemVerilog_3.1a.pdf .
The 3.1a standard is good enough for practical reference on language syntax etc. Though it is not the recommended getting started point, there are some engineers who would still like to reference the LRM time to time ( I know, I have actually met a few of those).